1. Field of the Invention
The present invention relates to a semiconductor device using shallow trench isolation technology.
2. Discussion of the Background
In recent years, a large scale integrated circuit (LSI) has been widely used in computers, communication systems and other electronic devices. The large scale integrated circuit includes a semiconductor chip in which a great number of transistors, resistors and other electrical components are formed and connected together so as to realize electric circuits in a semiconductor chip. This means that the performance of these electronic devices is greatly dependent upon the performance of the LSI. The performance of the LSI can be improved by achieving a scale down of the devices to realize high integration thereof.
Conventionally, an element isolation has been achieved by a LOCOS (local oxidation of silicon) technology. In the element isolation by the LOCOS separation, an encroachment of an oxide film called a "bird's beak" is formed in element formation regions, and thus effective areas in the element formation regions are reduced. Therefore, the element isolation by the LOCOS separation is not effective in high integration.
Recently, in consideration of such circumstances, an element isolation by a STI (Shallow Trench Isolation) technology has been frequently used. According to the STI technology, a shallow trench for element isolation is formed in a surface region of a semiconductor substrate, and the shallow trench is filled with an isolation film.
This technology of element isolation differs from the LOCOS separation in that the "bird's beak" is not generated. This serves to prevent element formation regions from being reduced. Moreover, the STI technology has an element isolation performance superior to that of the LOCOS separation. Thus, the element isolation by the STI technology is more suitable to high integration as compared with the element isolation by the LOCOS method.
However, a semiconductor device isolated by the STI technology has the following problems.
In the element isolation process according to the STI technology, first, as shown in FIG. 11A, a shallow trench 92 is formed in a surface region of a semiconductor substrate 91 on which a gate insulation film 94 is formed. Subsequently, an isolation film 93 is formed over the surface region of the semiconductor substrate with such a thickness that the element isolation trench 92 is sufficiently filled with the isolation film 93.
Next, the isolation film 93 thus formed is etched back to the surface of the semiconductor substrate by means of a CMP (Chemical and Mechanical Polishing) method, an isotropic etching, etc., so that the isolation film 93 formed on the substrate region except in the element isolation trench 92 is removed. As a result, the isolation film 93 remains only in the trench 92.
When the isolation film 93 is removed by means of etching, the isolation film 93 is subjected to over-etching to prevent the isolation film 93 from remaining on an element formation region surface (active layer surface). As a result, as shown in FIG. 11B, an upper portion of a side surface of the trench 92, i.e., an upper portion of the semiconductor substrate region configuring the trench 92, is exposed. The semiconductor substrate portion exposed at the upper portion of the side surface of the trench 92 is referred to hereinafter as an exposed trench portion.
The over-etching of the isolation film 93 has a further disadvantage that the element formation region surface (active layer surface) is also etched together with the isolation film 93, giving damage to the element formation region surface. In order to prevent such a disadvantage from occurring, the CMP method may be employed.
Specifically, a stopper film (not shown) is formed over the substrate surface on which the gate insulation film 94 is already formed, and thereafter, the element isolation trench 92 is formed. Subsequently, an isolation film 93 is formed over the substrate surface, and thereafter, the isolation film 93 is etched back to the stopper film by the CMP method. Next, the stopper film is removed. As a result, a stepped convex portion of the gate insulation film 94 is formed on the substrate surface. Then, the convex portion of the gate insulation film 94 is removed by etching to achieve planarization of the substrate surface.
In this case, however, it is difficult to attain uniform etching to the convex portion of the isolation film 93 over the substrate surface. Since this etching is generally attained by hydrofluoric acid isotropic etching, an exposed trench portion as shown in FIG. 11B is generated.
In this state, if an electrode, a wiring or a conductive component constituted of an electrode and a wiring (referred hereinafter to as an electrode wiring 95) is formed on the element formation region and the element isolation region, the exposed trench portion comes into contact with the electrode wiring 95, as shown in FIG. 11C. As a consequence, when a voltage is applied to the electrode wiring 95, a horizontally directed electric field E is generated with respect to the substrate surface, as shown in FIG. 11C. The generation of the electric field E affects the elements formed in the element formation regions, degrading the performance of the device. Basically, the electric field E should not be generated.
As an example, when a MOS transistor is formed in the element formation region, the electrode wiring 95 includes a gate electrode, a gate wiring or a conductive element constituted of the gate electrode and the gate wiring (referred to hereinafter as a gate electrode wiring), and the following problem arises.
FIG. 12 shows a plan pattern view of a background MOS transistor which is isolated by the STI separation. In FIG. 12, reference numeral 97 denotes element formation regions, and the remaining regions show element isolation regions which are isolated by the STI separation. That is, the element formation regions 97 are surrounded by shallow trenches for element isolation.
When a voltage is applied to the gate electrode wiring 95, not only is a vertically directed electric field generated, but a horizontally directed electric field is also generated by the voltage applied to the gate electrode wiring 95, in a semiconductor substrate portion of the element formation region in the vicinity of a contact portion 96 of the exposed trench portion and the gate electrode wiring 95. Such a semiconductor substrate portion of the element formation region, in which not only the vertically directed electric fields but also a different-way directed electric field are generated, is referred to hereinafter as a corner device.
As described above, since in the corner device not one-dimensional but two-dimensional electric fields are generated, a short channel effect easily occurs in a case in which a gate electrode width becomes small due to a scale down.
This means that a short channel effect is greater than in a case in which the exposed trench portion is not provided. In other words, it means that it is difficult to achieve high integration of the semiconductor elements due to a strong short channel effect, although it is possible to prevent spaces of the element formation region from being reduced with the use of STI technology.
For performing an experimental test, MOS transistors are formed in the element formation regions of a semiconductor substrate, the element separation region being isolated according to the background STI or LOCOS separation. FIG. 13 shows Vg-Id characteristic curves of the MOS transistor, obtained by the test results.
In FIG. 13, reference character "a" indicates a Vg-Id characteristic curve of a MOS transistor using the STI separation in which a short channel effect is not generated, reference character "b" indicates a Vg-Id characteristic curve of a MOS transistor using the STI separation in which the short channel effect is generated, and reference numeral "c" indicates a Vg-Id characteristic curve of a MOS transistor using the LOCOS separation in which a short channel effect is not generated. In FIG. 13, the ordinate (Id) is a logarithm scale.
In FIG. 13, when the drain currents Id of these MOS transistors are compared with each other with regard to a gate voltage Vg, it can be seen that the MOS transistors using the STI separation (whose characteristic curves are shown by reference numerals "a" and "b") have drain currents Id larger than the MOS transistors using the LOCOS separation (whose characteristic curves are shown by reference character "c"). This indicates that a threshold voltage shifts to a low level side due to a strong short channel effect in the MOS transistor using the STI separation.
To solve the above mentioned problem, there is proposed a method in which the width of the gate electrode wiring 95 is made large to lengthen the channel length. However, such a method not only hinders a scale down of devices but also lowers effects obtained from the use of the STI separation in place of the use of the LOCOS separation.
The problems as described above apply to a case (FIGS. 11B and 11C) in which the upper surface of the isolation film 93 filled in the element isolation trench 92 is flat, as well as a case (FIG. 14) in which the upper surface of the isolation film 93 is concaved along a circumference of a side wall on an upper portion of the element isolation trench 92.
Moreover, the STI separation differs from the LOCOS separation in that there is no reduction in space of the element formation region. However, the width of the element formation region becomes small accompanying with the progress of scale down. Accordingly, there has arisen a problem that it is difficult to make a contact to the element formation region.